Currently, receivers achieve synchronization of received signals such as minimum shift keyed (MSK) signals by using two Phase-Lock-Loops (PLL). For example, a conventional MSK modulation scheme having 1.2 kHz and 1.8 kHz frequencies typically incorporates a PLL at each frequency. Each PLL locks onto the received signal when the frequency matches its operating frequency. After locking, the PLLs continuously produce received information on the 1.2 kHz or 1.8 kHz signals respectively. This information is used to determine the bit boundaries of the incoming signal to enable synchronization of the receiver. In this way, the receiver can be continuously adjusted during the synchronization period to achieve and maintain synchronization.
However, with this PLL method, the end of the transmitted preamble (synchronization) signal may significantly affect the accuracy of the synchronization achieved. That is, by permitting continuous adjustment during the synchronization period, all changes in bit boundaries will cause a synchronization adjustment. Specifically, when the end of the preamble is very noisy, the inaccuracy in the adjustment in synchronization is more likely to substantially affect the synchronization achieved, because the incorrect adjustment occurs at the end of the adjustment period. Additionally, in a noisy signal environment, the wrong PLL may be updated because of the difficulty in determining the transition points between the two frequencies (i.e., when one frequency stops and the other frequency starts). Thus, a loss of synchronization may result. Also, the requirements on the memory and central processing unit (CPU) are extensive for implementing a PLL based synchronization scheme with a digital processor.
Thus, what is needed is a memory and CPU efficient techniques for synchronization that is less susceptible to localized noise, while achieving synchronization.